半導體測試廠面臨微利時代，處境艱難。應用資料探勘技術有助於其提升競爭力以利生存。本文中，提出一個混合式資料探勘模型 (classification rules) 以縮減半導體測試廠隨機存取動態記憶體 (dynamic random access memory, DRAM) 的測試項目以降低測試時間，並發掘決策法則。該模型混合了類神經網路 (neural network, NN) 與粗略集 (rough set theory, RST)。在此混合式模型中，類神經網路首先被應用來減少干擾因子 (測試項目)，接著粗略集被應用來找出基本且必要之測試項目 (reduct)，並發掘決策法則。經收集DDR266 DRAM 的實際測試資料進行驗證後，實驗結果顯示該混合模型能夠有效的降低測試項目、發掘決策法則，並同時維護良好的測試品質。詳言之，測試的項目可從52 項縮減到4 項；亦即測試時間可由176.52 秒減少到38.43 秒。同時，其辨識率仍可維持在98.57%之水準。此外，決策法則有助於測試工程師對瑕疵行為之分析與了解。

In this study a hybrid model combining artificial neural network (NN) approach with rough set theory (RST) is proposed for reducing the DRAM test items (testing time). This enables DRAM final testing firms to be more competitive in the fiercely competitive semiconductor industry. In this hybrid model, NN is first used to filter noise attributes (test items) and then RST is used to eliminate irrelevant attributes and eventually find decision rules and reduct(s), which includes a minimum set of attributes that can best distinguish data objects in a dataset. To investigate the effects of the hybrid model, a dataset of DDR266 DRAMs is collected from a real DRAM final testing firm for experiments. Experimental results show that this hybrid model has the potential to reduce DRAM test items (cost) significantly meanwhile maintaining a high discriminating accuracy. Specifically, the test time of a DRAM chip can be reduced from 176.52 seconds (52 items) to 38.43 seconds (4 items) with the overall discriminating accuracy meanwhile being maintained at 98.57%. The decision rules can be used to train testing engineers to better understand the fault behavior in a DRAM dataset.